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publication release date: april 2000 - 1 - revision a2 general description the w536xxxp, a member of viewtalk tm family, is a high-performance 4-bit micro-controller (uc) with built-in 8kw uc program. the 4-bit uc core contains dual clock source, 4-bit alu, two 8-bit timers, one 14 bits divider, maximum 32 pads for input or output, 8 interrupt sources and 8-level nesting for subroutine/interrupt applications. speech unit, integrated as a single chip with maximum 128 seconds (based on 6.4k sample rate with 5 bits mdpcm) , is capable of expanding to 512 seconds speech addressed by external memory w55xxx with serial bus interface. it can be implemented with winbond power speech using mdpcm algorithm. melody unit provides dual tone output and can store up to 1k notes. power reduction mode is also built in to minimize power dissipation. it is ideal for educational toys, remote controllers and other application products which incorporate both melody and speech. body w536030p w536060p w536090p W536120P voice 30 sec 60 sec 90 sec 120 sec i/o pad 8i/o, 8i (ra/rb/rc/rd) 8i/o, 8i (ra/rb/rc/rd) 8i/o, 12i, 12o (ra/rb/rc/rd/re/rf /rg/rh) 8i/o, 12i, 12o (ra/rb/rc/rd/re/rf /rg/rh) wdt disable/enable (mask option) y y y y sub-clock rc/xtal mode (mask option) y y y y tri-state serial bus (mask option)( 1) y y y y cascaded voice through serial bus (2) y y n y (1) tri-state serial bus mask option can float serial bus while voice playing is no active. let this mask option is disabled to get minimum power consumption in general. (2) cascaded voice rom user option help to expand voice up to 512 sec through serial bus by w55xxx chip . features ? operating voltage: 2.4 volt ~ 5.5 volt ? watch dog disabled/enabled by mask option ? dual clock operating system ? main clock with rc/crystal (400 khz to 4 mhz) ? sub-clock with 32.768 khz rc/crystal by mask option ? memory ? program rom (p-rom): 8 k 20 (rom bank0) ? data ram (w-ram): 1k 4 bit (ram bank 0 is 512 nibbles from 0:000~0:1ff and 0:380~0:3ff are mapped to special register. ram bank f is 512 nibbles from f:200~f:3ff either data ram or dedicated to script kernel ) ? maximum 32 input/output pads ? ports for input only: 12 pads (rc, rd and rg port ; rg for w536090p/120p only) ? ports for output only: 12 pads (re, rf and rh port; rh for w536090p/120p only) ? ports for input/output: 8 pads

publication release date:april 2000 - 2 - revision a2 ? power-down mode ? hold mode (except for 32khz oscillator) ? stop mode (including 32khz oscillator and release by rd or rc port) ? eight types of interrupts ? five internal interrupts (divider, timer 0, timer 1, speech, melody ) ? three external interrupts (port rc, rd, ra) ? one built-in 14-bit clock frequency divider circuit ? two built-in 8-bit programmable countdown timers ? timer 0: one of two clock sources (fosc/4 or fosc/1024) can be selected ? timer 1: built-in auto-reload function includes internal timer, external event counter from rc.0 ? built-in 18/14-bit watchdog timer for system reset. ? powerful instruction sets. ? 8-level subroutine (including interrupt) nesting ? speech function ? provided 1m / 2m/ 3m/ 4m bits voice rom for w536030p/060p/090p/120p based on 5 bits mdpcm algorithm ? voice rom (v-rom) available for uc data. ? maximum 8*256 label/interrupt vector (voice section number) available ? provide two types of speech busy flag to either each go or each trigger ? maximum up to 16m bits speech address capability interface with external memory w55 xxx through serial bus. ? melody function ? provide 1k notes (22bits/note) dedicated melody rom ? provide two types of melody busy flag to uc either each note or each song ? provide 6 kinds of beat, 16 kinds of tempo, and pitch range from g3# to c7 ? tremolo, triple frequency and 3 kinds of percussion available ? maximum 31 songs available ? can mix speech with melody ? multi-engine controller ? direct driving speaker/buzzer or dac output ? chip on board available

publication release date:april 2000 - 3 - revision a2 block diagram pc stack (8 levels) timer 0 (8 bit) timing generator xin xout timer 1 (8 bit) watch dog timer (18/14 bit) alu acc divider (14/10 bit) x32i x32o rom 8k*20bit ram 1k* 4bit interrupt ,hold & stop control special register hcf hef ief evf flag1 psr0 mr0 pef flag0 lpx3 pm0 lpx2 lpx0 lpx1 lpx4 lpx5 lpy0 lpy1 spc mld port re port ra tone ra0~3 re0~3 port rb port rd port re rb0~3 rd0~3 port rc rc0~3 port rg rg0~3 port rf rf0~3 port rh rh0~3 wrp mld_play mld_busy speech mdpcm core spc_play spc_busy pwm1/dac rosc parallel to serial rdp spdata vssp test voice rom (1m /2m/3m/4m bits) pwm/ dac mix block pwm2 vddp lpxy shared_rom data res vdda vssa vdd vss dual tone melody (1k notes)

publication release date:april 2000 - 4 - revision a2 pad description symbol i/o function xin/rxin i input pad for main clock oscillator. it can be connected to crystal when crystal mode is selected (scr0.2=1), otherwise connect a resistor to vdd to generate main system clock while rc mode is selected (scr0.2=0 and default). oscillator can be enabled or stopped by set scr0.1 to 1 or clear to 0 separately. external capacitor connects to start oscillation while crystal mode xout o output pad for oscillator which is connected to another crystal pad when in crystal mode. external capacitor connects to start oscillation when in crystal mode. x32i/rsub1 i 32.768 khz crystal input pad or external resistor node 1 by mask option . external 15~20pf capacitor connects to get more accurate clock when in crystal mode. x32o/rsub2 o 32.768 khz crystal output pad or external resistor node 2 by mask option. external 15~20pf capacitor connects to get more accurate clock when in crystal mode. ra0 ~ ra3/tone i/o general input/output port specified by pm1 register. if output mode is selected, pm0 register bit 0 can be used to specify cmos/nmos driving capability option. initial state is input mode. ra3 may be uses as tone if bit 0 of mr0 special register is set to logic 1. an interrupt source. rb0 ~ rb3 i/o general input/output port specified by pm2 register. if output mode is selected, pm0 register bit 1 can be used to specify cmos/nmos driving capability option. initial state is input mode. rc0 ~ rc3 i 4-bit schmitter input with internal pull high option specified by pm3 register bit 2. each pad has an independent interrupt capability specified by pefl special register. interrupt and stop mode wake up source. rc0 is also the external event counter source of timer1. rd0 ~ rd3 i 4-bit schmitter input port with internal pull high option specified by pm3 register bit 3. each pad has an independent interrupt capability specified by pefh special register. interrupt and stop mode wake up source. re0~re3 o output port only. pm3 register bit 0 can be used to specify cmos/nmos driving capability option. rf0~rf3 o output port only. pm3 register bit 1 can be used to specify cmos/nmos driving capability option. rg0 ~ rg3 i input port with internal pull high option specified by pm6 register bit 0. (w536090p/W536120P only) rh0 ~ rh3 o output port only. pm6 register bit 1 can be used to specify cmos/nmos driving capability option. (w536090p/W536120P only) res i system reset pad, active low with internal pull-high resistor. test i test pad. active high with internal pull low resistor. rosc i connect resistor to vdd pad to generate speech or melody playing clock source. pwm1/dac o while speech or melody is active, pwm1/dac is speaker direct driving output or dac output controlled by voice output file. pwm2 o while speech or melody is active, pwm2 is another speaker direct driving output. wrp o external serial memory address write clock for voice extension.

publication release date:april 2000 - 5 - revision a2 rdp o external serial memory address read clock for voice extension. spdata i/o external serial memory data in/out for voice extension. vss i chip ground. vssp i chip ground for pwm or dac playing output. vssa (3) i chip ground. (w536090p/120p only) vdd i power source. vddp i power source for pwm or dac playing output. vdda (3) i power source. (w536090p/120p only) (3) vdda, vssa for w536090p/120p only. to sure chip operation properly, please bond all vdd, vdda, vddp, vss, vssa and vssp pads, and connect vss, vssp form chip external pcb circuit. absolute maximum ratings parameter rating unit supply voltage to ground potential -0.3 to +7.0 v applied input/output voltage -0.3 to +7.0 v power dissipation 120 mw ambient operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (vdd ? vss = 3.0v, f m = 4 mhz with rc mode, fs = 32.768 khz, with xtal mode, t a = 25 c unless otherwise specified) parameter sym. conditions min typ max unit op. voltage v dd 2.4 5.5 v op. current i op1 dual clock with crystal - 400 500 ua (no load, no voice, no dual clock with rc type 400 500 melody) sub-clock only 15 30 hold mode current i op2 sub-clock active only 4 6 ua stop mode current i op3 1 ua rdp/wrp output high current io h1 vout =2.7v -0.8 ma rdp/wrp output low current io l1 vout =0.4v 0.8 ma input low voltage v il - vss - 0.3 vdd input high voltage v ih - 0.7 - 1 vdd port ra, rb, re,rf and rh output low voltage v abl iol = 2.0 ma - - 0.4 v port ra, rb, re,rf and rh output high voltage v abh ioh = -2.0 ma 2.4 - - v

publication release date:april 2000 - 6 - revision a2 pull-up resistor r cd port rc, rd, rg 200 300 400 k ? res pull-up resistor r res - 50 100 200 k ? pwm1/2 source current (4) i sph volume option =00 -20 ma (r load =8 ? between pwm1 volume option =01 -70 and pwm2 ) volume option =10 -110 volume option =11 -135 pwm1/2 sink current (4) i spl volume option =00 20 ma (r load =8 ? between pwm1 volume option =01 70 and pwm2 ) volume option =10 110 volume option =11 135 dac output current i dac vdd=3v, rl=100ohm -4 -5 -6 ma (4) pwm current deviation will be 20%. ac charateristics (vdd ? vss = 3.0v, f m = 4 mhz with rc mode, fs = 32.768 khz, with xtal mode, t a = 25 c unless otherwise specified) parameter sym. conditions min. typ. max. unit sub-clock frequency f sub crystal type and x32in and x32o with 17pf external cap. 32768 hz main-clock frequency f m rc type/crystal type 400k - 4m hz chip operation frequency f osc scr0.0=1,f sys = f sub 32768 hz scr0.0=0;f sys = f main 400k - 4m instruction cycle time t cyc one machine cycle - 4/f osc - s reset active width t raw fosc = 32.768 khz 1 - - s interrupt active width t iaw fosc = 32.768 khz 1 - - s main clock rc frequency f rxin rxin =680k ? 1m hz rxin =330k ? 2m rxin =200k ? 3m rxin =130k ? 4m sub-clock ring oscillator f rsub r sub =680k ? 32 khz sub-clock oscillation stable time @ cold start f stop r sub =680k ? 0.8 1 s frequency deviation of main-clock f rxin 2 mhz ? f f f(3v) f(2.4v) f(3v) ? 10 % frequency deviation of main-clock f rxin = 3 mhz ? f f f(3v) f(2.4v) f(3v) ? 15 % frequency deviation of main-clock f rxin = 4 mhz ? f f f(3v) f(2.4v) f(3v) ? 20 % rosc frequency f rosc r osc =680k ? 3 mhz frequency deviation of f rosc = 3mhz ? f f f(3v) f(2.4v) f(3v) ? 7.5 % (5) the deviation will be +20% while vdd drops from 5.5v to 2.4v based on same resistor

publication release date:april 2000 - 7 - revision a2 iop vs. main clock rc mode 0 200 400 600 800 1234 freq (mhz) iop (ua) 3v 4. 5v oscillation freq vs. sub-clock 20 24 28 32 36 40 44 560 620 680 750 820 1k rsub (kohm) fsub (khz) 3v 4. 5v

publication release date:april 2000 - 8 - revision a2 main freq vs. rxin 0 1 2 3 4 5 6 130 150 160 200 330 680 2k 3k rxin (kohm) fmain (mhz) 2.4v 3v 4.5v 5.5v voice operating freq. vs. rosc 2 2. 5 3 3. 5 4 4. 5 470 560 680 910 rosc (kohm) freq (mhz) 3v 4. 5v

publication release date:april 2000 - 9 - revision a2 application circuit--1: sub clock with rc mode w536xxxp rc0~3 rd0~3 ra0~3 rb0~3 re0~3 x32in x32o battery r4 c1 vdd vddp r1 r3 rosc xin vssp vss res c3 vddp pwm2 pwm1/dac rf0~3 ( *1) r5 470 (*2) vdd c2 spdata rdp wrp w55m08 rg0~3 rh0~3 r2 vdda vssa component c1 c2 c3 r1 r2 r3 r4 value 0.1uf 4.7uf 0.1uf 680k 680k 680kohm/1mhz 330kohm/2mhz 200kohm/3mhz 130kohm/4mhz 100 note: (1) option r5 equals to 100 ? if high noise immunity is needed. (2) for dac option application (3) to sure chip operation properly, please bond all vddp, vdd, vdda, vssp, vssa and vss (4) vdda, vssa are only for w536090p/120p.

publication release date:april 2000 - 10 - revision a2 application circuit--2: sub clock with xtal mode component c1 c2 c3 c4~c5 r1 r3 r4 value 0.1uf 4.7uf 0.1uf 17pf~20pf 680k 680kohm/1mhz 330kohm/2mhz 200kohm/3mhz 130kohm/4mhz 100 note: (1) option r5 equals to 100 ? if high noise immunity is needed. (2) for dac option application. (3) to sure chip operation properly, please bond all vddp, vdd, vdda, vssp , vssa and vss . (4) vdda and vssa are only for w536090p/120p. w536xxxp rc0~3 rd0~3 ra0~3 rb0~3 re0~3 32.768khz c4 x32in x32o battery r4 c1 vdd vddp r1 r3 rosc xin vssp vss res c3 vddp pwm2 pwm1/dac rf0~3 (*1) r5 470 (*2) vdd c2 c5 spdata rdp wrp w55m08 rg0~3 rh0~3 vssa vdda

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